The present invention relates to a technology for allowing a CPU (central processing unit) or other bus master to access a peripheral I/O device or other bus slave coupled to a bus. More specifically, the present invention relates to a microcomputer that provides control to let a bus master access a bus slave in an efficient manner.
In recent years, semiconductor integrated circuits are integrated to an increasingly high degree so that plural bus masters, such as CPUs, and plural bus slaves, such as peripheral I/O devices, are now integrated into a single semiconductor chip. In such semiconductor devices, the bus slaves, such as peripheral I/O devices and external buses, operate at frequencies lower than operating frequencies of the bus masters so that the communication between the bus masters and bus slaves is generally established by performing clock domain conversion with a synchronization signal.
Further, when a bus master writes data to a bus slave coupled to a bus, a write buffer can be used to improve cycle performance.
Furthermore, if, in a system where plural bus masters access a bus slave through a bus, there is a conflict between bus access requests from the bus masters, arbitration is generally performed in accordance with a predetermined order of priority. Technologies related to the above arbitration are described by inventions disclosed, for instance, in Japanese Unexamined Patent Publications No. 2009-169539 and 2002-163032.
The invention disclosed in Japanese Unexamined Patent Publication No. 2009-169539 provides a microcomputer that is capable of establishing serial communication even in a sleep mode. The invention includes a serial communication unit. In addition to a main clock that is generated in a normal operation mode of a CPU, the serial communication unit generates a subclock in a sleep mode in which the power consumption is smaller than in the normal operation mode, operates in accordance with the subclock in the sleep mode, and establishes serial communication with a peripheral circuit. The invention also includes a wake-up factor identification unit and a wake-up signal output unit. The wake-up factor identification unit judges, in accordance with received data, whether a wake-up factor is generated. The wake-up factor demands a wake-up process for switching an operation mode from the sleep mode to the normal operation mode. The wake-up signal output unit outputs a wake-up signal to an operation mode switching unit when it is judged that the wake-up factor is generated. The wake-up signal switches the operation mode from the sleep mode to the normal operation mode.
The invention disclosed in Japanese Unexamined Patent Publication No. 2002-163032 provides a data processor that not only permits a quick transition from a low power consumption state to an operating state, but also assures low power consumption. The data processor has a standby mode, a write standby mode, and a sleep mode. In the sleep mode, the supply of a synchronization clock signal to a CPU shuts off so that the synchronization clock signal is supplied to the other circuit modules. In the standby mode, the multiplication and frequency division operations of a clock pulse generator are stopped with the synchronization clock signal supply to the other circuit modules shut off. In the write standby mode, the multiplication and frequency division operations of the clock pulse generator are enabled with the synchronization clock signal supply to the CPU and other circuit modules shut off. The write standby mode allows the CPU to switch into a command execution state more quickly than the standby mode and consumes less power than the sleep mode.